The invention relates to a frequency splitter circuit. Frequency splitters are digital circuits in which the input frequencies are whole-number multiples of the output frequencies. The simplest frequency splitter consists of a bi-stable binary scaler, which splits the input frequency in a ratio of 2:1.
Frequency splitters are typically realized with master-slave flip-flops. An example of this type of frequency splitter circuit is described in Halbleiterschaltungstechnik (Tietze, Schenk, 10th ed.: 235-40). However, at least three transistor levels are arranged on top of one another between two supply potentials in these known frequency splitter circuits, so that relatively large supply voltages are needed to supply these known frequency splitter circuits, and only relatively small signal amplitudes can be achieved therewith.
But the high growth rates for mobile electrically operated devices, including in the field of communications or entertainment electronics, demand circuits which are suitable for ever smaller supply voltages and which exhibit a small current consumption.
It is accordingly an object of the invention to provide a frequency splitter circuit which overcomes the above-mentioned disadvantageous of the prior art apparatus of this general type. In particular, it is an object of the invention to provide such a frequency splitter circuit that is suitable for low supply voltages and with which large signal amplitudes can be achieved.
With the foregoing and other objects in view there is provided, in accordance with the invention, a frequency splitter circuit, that includes: a clock input for receiving a clock input signal having a frequency; a main output providing a clock output signal having a frequency that is split relative to the frequency of the clock input signal; an auxiliary output providing a clock output signal having a frequency that is split relative to the frequency of the clock input signal; a first differential amplifier having an input coupled to the auxiliary output and having an output coupled to the main output; and a second differential amplifier having an input coupled to the main output and having an output coupled to the auxiliary output. The first differential amplifier and the second differential amplifier are coupled with the clock input.
The described frequency splitter circuit includes two differential amplifiers, one of which is active, depending on the clock input signal. The clock output signals, which are derivable at the main and auxiliary outputs, respectively, are phase-shifted 90xc2x0 relative to each other. Since the described frequency splitter circuit requires only two differential amplifiers, it can be realized with a small current consumption. In addition, the differential amplifiers, and thus the frequency splitter circuit, are suitable for operation with small supply voltages. At the same time, the differential amplifiers enable the output clock signals to have large signal amplitudes.
In accordance with an added feature of the invention, the first differential amplifier includes means for providing an inverted signal, and the second differential amplifier includes means for providing a non-inverted signal. The first differential amplifier provides the signal of the auxiliary output, which is available on the input side (input of the first differential amplifier), in inverted form on the output side (output of the first differential amplifier) at the main output. The second differential amplifier provides the signal of the main output, which is available on the input side (input of the second differential amplifier), in non-inverted form on the output side (output of the second differential amplifier) at the auxiliary output. The first and second differential amplifiers are alternately active in dependence upon the clock input signal. The means for providing inverted or non-inverted signals can be constructed rather simply, for instance by poling terminal pairs, if the clock output signals are present as differential signals, and main and auxiliary outputs are realized with corresponding terminal pairs.
In accordance with an additional feature of the invention, the differential amplifiers include means for holding a signal on the input side. In addition to providing an inverted or non-inverted signal, the differential amplifiers can include means for holding the respective signal on the input side. The first differential amplifier holds the clock output signal at the auxiliary output, and the second differential amplifier holds the clock output signal at the main output. When the differential amplifiers have inverting characteristics without additional wiring, the holding means can be realized rather simply if the clock output signals are present as differential signals.
In accordance with another feature of the invention, there is provided an embodiment in which the first and second differential amplifiers are each connected to a current source, which can be switched with the aid of the clock input signal. The current sources can alternately activate first and second differential amplifiers in dependence upon the clock input signal. The frequency splitter circuit, which includes switchable current sources has a particularly simple circuit structure. The current sources can be connected to the differential amplifiers on the reference potential side, giving the circuit characteristics substantial independence from oscillations of the supply voltage supplying the frequency splitter.
In accordance with a further feature of the invention, the first and second differential amplifiers are each connected to an emitter follower, which is switchable with the aid of the clock input signal. This way, the differential amplifiers can be cut off particularly rapidly, and large edge steepnesses of the clock output signals are possible.
In addition, this embodiment is suitable for particularly small supply voltages and large signal amplitudes at the output.
In accordance with a further added feature of the invention, an emitter follower is coupled to each of the differential amplifiers on the input side for coupling with the main and auxiliary outputs. This way, the amplitudes of the clock output signal can be increased still further. This also produces still greater edge steepness, which reduces the phase noise of the frequency splitter circuit. The emitter followers thus act as impedance converters.
In accordance with a further additional feature of the invention, the differential amplifiers each include four emitter-coupled npn transistors, whose emitter terminals are coupled with the input. Of the four emitter-coupled transistors, two can be provided for providing the inverted or non-inverted signal to the differential amplifiers on the output side, and two can be provided for holding a signal which is pending at the differential amplifier on the input side.
In accordance with a concomitant feature of the invention, the clock input signal can be supplied to the emitter terminals of the transistors of the first differential amplifier in non-inverted form, and to the emitter terminals of the transistors of the second differential amplifier in inverted form.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in frequency splitter circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.